1. Field of the Invention
The present invention relates to a semiconductor package wherein an interposer (wiring base material) that is provided with a wiring layer having a prescribed wiring pattern on an insulating base material is adhered to an electrode formation surface of a semiconductor chip by means of an adhesive layer; the wiring layer and electrodes of the semiconductor chip connect by way of bump contacts (bump electrodes); i.e., are electrically connected by the flip-chip method; and external connectors are provided on the surface of the wiring layer that is opposite from the surface that is joined to the semiconductor chip. The present invention also relates to a fabrication method of such a semiconductor package.
2. Description of the Related Art
The research and development of higher-density semiconductor device packages is currently making great strides, and many configurations and methods have been proposed for the configuration of a package. In particular, a high-density semiconductor package known as a Chip Scale Package (CSP) in which the package size has been miniaturized to a size that is substantially equal to chip size is receiving attention, and a variety of developments have been achieved.
The form of a semiconductor package that is suitable for constructing a CSP is:
a semiconductor package in which an interposer, in which a wiring layer of, for example, copper wiring having a prescribed wiring pattern is arranged on an insulating base material such as polyimide tape, is adhered to the electrode formation surface of a semiconductor chip by way of an adhesive layer; electrodes, such as aluminum electrodes, of the semiconductor chip are electrically connected to a wiring layer by way of bumps such as gold ball bumps; i.e., by the so-called flip-chip method; and external connectors are provided on the side of the wiring layer that is opposite from the junction surface with the semiconductor chip. In this case, external connectors are, for example, solder balls that are attached to lands of the wiring layer or similar lands.
Semiconductor packages of the prior art having this type of construction can be classified into two types according to the positional relation between the semiconductor chip, the insulating base material, the wiring layer, and the adhesive layer. The first type is characterized by a configuration in which the positioning order is: semiconductor chip, adhesive layer, insulating base material, and wiring layer. The second type is a configuration in which the positioning order is: semiconductor chip, adhesive layer, wiring layer, and insulating base material.
Prior art that belongs to the first type is disclosed in the explanation pertaining to FIG. 2 and FIG. 4 of Japanese Patent Laid-open No. 321157/95, and in the explanation pertaining to FIG. 4 and FIG. 9 of Japanese Patent Laid-open No. 102474/96. Prior art that belongs to the second type is disclosed in the explanation pertaining to FIG. 1 and FIG. 3 of Japanese Patent Laid-open No. 321157/95, and in the explanation pertaining to FIG. 3 and FIG. 8 of Japanese Patent Laid-open No. 102474/96.
Turning now to the accompanying figures, explanation is next presented regarding the construction and fabrication method of semiconductor packages of the above-described first type and second type.
FIG. 1 shows a sectional view of semiconductor package 2 of one example of the prior art, and FIG. 2 is an enlarged view of portion B in FIG. 1.
This semiconductor package 2 of the prior art is the above-described first type of semiconductor package and has a construction in which semiconductor chip 21 is applied to wiring tape 5 by means of adhesive layer 26. As shown in FIG. 2, this portion is constructed by laminating in the order: semiconductor chip 21, adhesive layer 26, insulating film 23 as the insulating base material, copper wiring 24 as the wiring layer, and cover resist 29 that insulates and covers copper wiring 24.
Chip electrodes 22 and copper wiring 24 are electrically connected by way of filled copper bumps 27 that fill holes that are formed in adhesive layer 26 and insulating film 23. Gold plating (not shown in the figures) is applied to the contacting surfaces of chip electrodes 22 and filled copper bumps 27 to form gold-gold metal junctions. Cover resist 29 is provided with holes 29b at positions where solder balls 28 are attached as the external terminals, and is provided with holes 29a at positions that correspond to chip electrodes 22. Solder balls 28 contact copper wiring 24 at holes 29b. Reinforcement resin 30 is formed on wiring tape 5 around the periphery of semiconductor chip 21.
When assembling semiconductor package 2, the adhesive surface that is formed by adhesive layer 26 of wiring tape 5 is temporarily secured on the electrode formation surface of semiconductor chip 21 on which chip electrodes 22 are formed; bonding tool 50 is passed through holes 29a and placed in contact with copper wiring 24, and pressure and ultrasonic waves are applied to the connector portion (inner lead connectors) chip electrode 22 and filled copper bumps 27. In a case in which semiconductor chip 21 is provided with, for example, 1000 chip electrodes 22, this bonding operation by means of bonding tool 50 must be carried out a total of 1000 times.
Next, complete adhesion between semiconductor chip 21 and wiring tape 5 can be obtained by applying appropriate heat and pressure to adhesive layer 26.
The construction and method of fabricating a semiconductor package of the second type is next explained with reference to the figures. FIG. 3 shows a sectional view of semiconductor package 3 of an example of the prior art, and FIG. 4 shows an enlarged view of portion C in FIG. 3.
This prior-art semiconductor package 3 is a semiconductor package of the second type, and has a construction in which semiconductor chip 31 and wiring tape 6 having adhesive layer 36 are adhered together. As shown in FIG. 4, a section of this semiconductor package 3 is of a construction in which semiconductor chip 31, adhesive layer 36, copper wiring 34 as the wiring layer, and insulation film 33 as insulating base material are laminated in that order. In contrast with semiconductor package 2 of the first type, copper wiring 34 is covered by insulating film 33 and adhesive layer 36, and a cover resist is therefore not used.
Chip electrodes 32 and copper wiring 34 are electrically connected by way of gold ball bumps 37 that are inserted into holes that are formed in adhesive layer 36. Gold plating (not shown in the figures) is applied to the surfaces of copper wiring 34 that contact the gold ball bumps so as to form a gold-gold metal junction. In insulating film 33, holes 33b are provided at the positions at which solder balls 38 are arranged as external terminals, and holes 33a are provided at positions that correspond to chip electrodes 32. Solder balls 38 contact copper wiring 34 in holes 33b. 
When assembling semiconductor package 3, the adhesive surface that is arranged on adhesive layer 36 of wiring tape 6 is temporarily secured to the electrode formation surface of semiconductor chip 31 upon which gold ball bumps 37 are arranged at chip electrodes 32, i.e., temporarily secured on the surface on which chip electrodes 32 are formed; and bonding tool 50 is passed through holes 33a and placed against copper wiring 34, following which pressure and ultrasonic waves are applied to the connectors (inner lead connectors); i.e., between gold ball bumps 37 and chip electrodes 32 and between gold ball bumps 37 and copper wiring 34. In a case in which, for example, 1000 chip electrodes 32 are provided on semiconductor chip 31, this bonding operation by bonding tool 50 must be performed a total of 1000 times.
An appropriate degree of heat and pressure are then applied to adhesive layer 36 to obtain complete adhesion between semiconductor chip 31 and wiring tape 6.
In the publications of Japanese Patent Laid-open No. 321157/95 and Japanese Patent Laid-open No. 102474/96, bonding is achieved when assembling the semiconductor package by first carrying out single-point bonding, which is the bonding operation by means of bonding tool 50, and then applying pressure and heat.
The semiconductor packages and the methods of their fabrication of the prior art that are disclosed in Japanese Patent Laid-open No. 321157/95 and Japanese Patent Laid-open No. 102474/96 have the following problems.
Semiconductor package 2 of the prior art necessitates the use of a cover resist, and moreover, necessitates the formation of filled bumps in holes that are formed in the adhesive layer and insulating base material. These requirements result in an increase in the number of steps as well as an increase in cost. Furthermore, with the current advances in miniaturization of semiconductor devices, the extremely small size of holes that are to be filled with bumps complicates the formation of the filled bumps. As a result, there are the problems of decreases in both yield and the reliability of connection between the wiring layer and filled bumps.
Prior-art semiconductor package 3, on the other hand, does not require the use of a cover resist, and to this extent, semiconductor package 3 requires fewer steps than semiconductor package 2. However, semiconductor package 3 still entails the burden of a process for forming holes 33a in the insulating base material for the insertion of the bonding tool.
In particular, since the insulating base material is harder than the adhesive layer, the process of opening holes in the insulating base material is a more burdensome process.
Furthermore, both examples of the prior art employ the application of ultrasonic waves and pressure by a bonding tool for each chip electrode (single-point bonding) to realize connection in the process of bonding the electrodes of the semiconductor chip and the wiring layer through the use of bumps according to the flip-chip method. There is consequently the problem that the more pins used by a semiconductor chip, the more time and labor that are required, and the higher the fabrication cost.
Finally, in both examples of the prior art, the process of adhering together the semiconductor chip and the wiring tape; i.e., the interposer, is separate from the process of bonding that connects the wiring layer and the electrodes of the semiconductor chip. There is consequently the problem that the adhering process also entails time and labor and increases the fabrication cost.
The present invention was realized with the object of solving the problems of the above-described prior art, and has as an object the provision of a semiconductor package, as well as a method of fabricating the semiconductor package, that enables a large reduction in both the number of steps and the amount of time required for the steps, that enables an improvement in fabrication yield, and moreover, that is highly reliable; this semiconductor package being a semiconductor package in which: an interposer, in which a wiring layer having a prescribed wiring pattern is arranged on an insulating base material, is adhered to the electrode formation surface of a semiconductor chip by means of an interposed adhesive layer; the electrodes of the semiconductor chip and the wiring layer are electrically connected by means of interposed bumps according to the flip-chip method; and external connectors are provided on the surface of the wiring layer that is on the opposite side from the surface that is adhered to the semiconductor chip.
According to the semiconductor package of a first invention of the present application for solving these problems, in a semiconductor package in which:
an interposer, in which a wiring layer having a prescribed wiring pattern is arranged on an insulating base material and an adhesive layer in which holes are formed is arranged on the wiring layer, and a semiconductor chip, in which bumps are affixed to electrodes, are adhered together such that the adhesive layer confronts the electrode formation surface of the semiconductor chip; moreover,
the bumps are inserted into the holes and the electrodes of the semiconductor chip and the wiring layer are electrically connected by way of the bumps according to the flip-chip method; and
external connectors are provided on the surface of the wiring layer that is opposite from the surface that is adhered to the semiconductor chip;
wherein the wiring layer is supported by an insulating base material within a range corresponding to the electrodes of the semiconductor chip.
Therefore, according to the semiconductor package of the first invention of this application, the wiring layer is supported by the insulating base material within at least the range corresponding to the electrodes of the semiconductor chip, thereby enabling suitable fabrication by the fabrication method of the invention as described hereinbelow and offering the advantage of reducing the number of steps and reducing the time required for the steps. In addition, the burden of the process of forming holes in the insulating base material is alleviated because the number of locations in the insulating base material in which holes are formed is reduced.
Furthermore, the bumps are inserted into holes that are provided in the adhesive layer and the chip electrodes and wiring layer are electrically connected by way of these bumps according to the flip-chip method. As a result, the first invention has the advantages of improving the reliability of connections between the chip electrodes and the wiring layer, sealing the junction surface between the semiconductor chip and the interposer by means of the adhesive, and further, improving both fabrication yield and reliability.
The method of fabricating the semiconductor package of the first invention of the present application is described below as the second invention of the present application.
The second invention of the present application is a method of fabricating a semiconductor package comprising steps of:
arranging bumps on electrodes of a semiconductor chip;
fabricating an interposer by forming a wiring layer having a prescribed wiring pattern on an insulating base material, forming an adhesive layer on the surface on which the wiring layer is arranged, and then providing holes at positions that will confront electrodes of the semiconductor chip when the semiconductor chip is mounted;
mounting the semiconductor chip on the interposer by placing the surface of the semiconductor chip in which the electrodes are formed in confrontation with the surface of the interposer on which the adhesive layer is formed and then inserting the bumps into the holes; and
realizing metal junctions between the wiring layer and bumps and adhering the semiconductor chip and interposer by means of the adhesive layer by applying heat to inner lead connectors that include the adhesive layer and bumps while pressing the interposer against substantially the entire surface of the semiconductor chip on which the electrodes are formed.
Thus, according to the semiconductor package and method of fabricating a semiconductor package of the second invention of the present application, metal junctions are realized between the wiring layer and the bumps, and bonding is realized between the semiconductor chip and the interposer by means of the adhesive layer by applying heat to the inner lead connectors that include the adhesive layer and the bumps while pressing the interposer against substantially the entire surface of the semiconductor chip on which the electrodes are formed. As a result, inner lead bonding of all electrodes on the semiconductor chip, bonding of the semiconductor chip and interposer, and sealing of the junction surfaces are accomplished all at once, thereby realizing the advantages of both greatly decreasing the number of steps and greatly reducing the amount of time required by the steps in the fabrication of the semiconductor package.
In a case in which 1000 electrodes are provided on a semiconductor chip, for example, the single-point bonding method of the prior art requires a total of 100 seconds to complete the process at the rate of 0.1 seconds to bond a single electrode. According to the present invention, however, not only all bonding but adhesion as well are completed in just a few seconds, thereby realizing a great advantage in terms of both time and economy.
Furthermore, providing an adhesive layer on the surface of the interposer on which the wiring layer is arranged, and then providing holes in the adhesive layer at positions that will confront the electrodes of the semiconductor chip obtains the advantage of preventing the entrapment of air under the adhesive layer.
In addition, mounting the semiconductor chip on the interposer by inserting the bumps into the holes of the adhesive layer obtains the advantage that positioning is extremely easy and reliable.
If, for example, a method of the prior art is adopted in which a semiconductor chip, an interposer that lacks an adhesive layer, and an adhesive sheet having holes are used and in which the semiconductor chip and the interposer are positioned, following which the adhesive sheet is sandwiched between the semiconductor chip and the interposer with the holes of the adhesive sheet positioned over the bumps that have been added on the chip electrodes, and then caused to adhere; not only is there the concern that air or other substances may be trapped under the adhesive layer, but assembly and positioning are extremely problematic and perhaps impossible in the case of miniaturization of the semiconductor device.
A laser processing method, plasma etching method, or lithographic method may be used for carrying out the micro-processing of holes.
In addition, in the method of fabricating the semiconductor package, a plurality of semiconductor chips may be mounted on a uniform interposer, following which individual semiconductor packages are separated. This method of fabricating semiconductor packages has the advantage of allowing not only inner lead bonding of all electrodes on a plurality of semiconductor chips, but bonding and sealing of the junction surfaces of the plurality of semiconductor chips and interposers to be performed all at once, thereby simultaneously obtaining a plurality of semiconductor packages and greatly reducing the number of steps and the time required for the steps in the fabrication of semiconductor packages.
In a case of mounting 30 semiconductor devices each provided with 1000 electrodes, the single-point bonding method of the prior art requires a total of 3000 seconds to complete the process at the rate of 0.1 seconds to bond a single electrode. The present invention, in contrast, completes not only all bonding but, in addition, completes sealing in just 10xcx9c20 seconds, thereby realizing an advantage in terms of both time and economy.
In the method of fabricating a semiconductor package, the pressure of the level surface of a heated pressure part against the rear surface of the semiconductor chip may be used to heat the inner lead connectors that include the adhesive layer and bumps while pressing the interposer against substantially the entire surface of the electrode formation surface of the semiconductor chip.
This method has the advantage of easily realizing inner lead bonding and adhesion. For example, a large number of semiconductor packages can be fabricated in a short time by using a heater plate to press a large number of semiconductor chips mounted on a uniform interposer.
The method of fabricating a semiconductor package may be realized by mounting a plurality of semiconductor chips on a uniform interposer, arranging this interposer on a silicon sheet, and then applying heat and pressure by a heater plate from above the semiconductor chips within a vacuum.
In the method of fabricating a semiconductor package, the conditions for applying heat and pressure to cause adhesion and the conditions for applying heat and pressure for obtaining the metal junction may be set substantially equal.
This method enables the application of heat and pressure that is neither insufficient nor excessive to both the adhesive layer and the inner lead connectors. This has the advantages of enabling satisfactory states of both adhesion and metal junction and enabling a further shortening of the time required for fabrication steps.
In the method of fabricating a semiconductor package, a thermoplastic resin may be used as the adhesive layer.
The use of a thermoplastic resin in the adhesive layer enables the easy separation of the semiconductor chips from the wiring substrate by reheating. This has the advantage of enabling the individual exchange of defective articles even after a large number of semiconductor chips have been adhered to a uniform interposer.